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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [clk_and_reset.v] - Rev 22

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Rev Log message Author Age Path
21 reg -> wire in and or mux in logic unneback 4856d 07h /versatile_library/trunk/rtl/verilog/clk_and_reset.v
18 naming convention vl_ unneback 4857d 18h /versatile_library/trunk/rtl/verilog/clk_and_reset.v
17 unneback 4921d 08h /versatile_library/trunk/rtl/verilog/clk_and_reset.v
4 added counters unneback 4948d 13h /versatile_library/trunk/rtl/verilog/clk_and_reset.v
3 various updates
counter added
unneback 4951d 09h /versatile_library/trunk/rtl/verilog/clk_and_reset.v

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