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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [clk_and_reset.v] - Rev 25

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Rev Log message Author Age Path
21 reg -> wire in and or mux in logic unneback 3569d 12h /versatile_library/trunk/rtl/verilog/clk_and_reset.v
18 naming convention vl_ unneback 3571d 00h /versatile_library/trunk/rtl/verilog/clk_and_reset.v
17 unneback 3634d 13h /versatile_library/trunk/rtl/verilog/clk_and_reset.v
4 added counters unneback 3661d 19h /versatile_library/trunk/rtl/verilog/clk_and_reset.v
3 various updates
counter added
unneback 3664d 14h /versatile_library/trunk/rtl/verilog/clk_and_reset.v

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