OpenCores
URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [defines.v] - Rev 100

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
100 added cache mem with pipelined B4 behaviour unneback 3735d 02h /versatile_library/trunk/rtl/verilog/defines.v
98 work in progress unneback 3739d 01h /versatile_library/trunk/rtl/verilog/defines.v
97 cache is work in progress unneback 3740d 17h /versatile_library/trunk/rtl/verilog/defines.v
94 clock domain crossing unneback 3745d 18h /versatile_library/trunk/rtl/verilog/defines.v
92 wb b3 dpram with testcase unneback 3746d 02h /versatile_library/trunk/rtl/verilog/defines.v
83 new BE_RAM unneback 3749d 04h /versatile_library/trunk/rtl/verilog/defines.v
76 dependency for wb3 to avalon bus unneback 3753d 03h /versatile_library/trunk/rtl/verilog/defines.v
75 added wb to avalon bridge unneback 3753d 03h /versatile_library/trunk/rtl/verilog/defines.v
62 WB_B3_RAM_BE updates, bte port map + define dependency unneback 3800d 01h /versatile_library/trunk/rtl/verilog/defines.v
61 WB_B3_RAM_BE updates, bte port map + define dependency unneback 3800d 02h /versatile_library/trunk/rtl/verilog/defines.v
60 added wb b3 byte enable memory, added test in makefile through icarus, typo in latch fixed unneback 3801d 21h /versatile_library/trunk/rtl/verilog/defines.v
59 added WB RAM B3 with byte enable unneback 3802d 21h /versatile_library/trunk/rtl/verilog/defines.v
49 added WB_B4RAM with byte enable unneback 3834d 04h /versatile_library/trunk/rtl/verilog/defines.v
48 wb updated unneback 3840d 22h /versatile_library/trunk/rtl/verilog/defines.v
44 added target independet IO functionns unneback 3941d 20h /versatile_library/trunk/rtl/verilog/defines.v
43 added logic for parity generation and check unneback 3945d 23h /versatile_library/trunk/rtl/verilog/defines.v
42 updated mux_andor unneback 3949d 23h /versatile_library/trunk/rtl/verilog/defines.v
40 new build environment with custom.v added as a result file unneback 3950d 01h /versatile_library/trunk/rtl/verilog/defines.v

powered by: WebSVN 2.1.0

© copyright 1999-2021 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.