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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [defines.v] - Rev 124

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115 shadow ram dependencies unneback 4577d 23h /versatile_library/trunk/rtl/verilog/defines.v
114 shadow ram dependencies unneback 4577d 23h /versatile_library/trunk/rtl/verilog/defines.v
113 shadow ram dependencies unneback 4577d 23h /versatile_library/trunk/rtl/verilog/defines.v
112 shadow ram dependencies unneback 4577d 23h /versatile_library/trunk/rtl/verilog/defines.v
108 WB_DPRAM unneback 4578d 18h /versatile_library/trunk/rtl/verilog/defines.v
104 cache unneback 4584d 00h /versatile_library/trunk/rtl/verilog/defines.v
103 work in progress unneback 4585d 12h /versatile_library/trunk/rtl/verilog/defines.v
101 generic WB memories, cache updates unneback 4586d 19h /versatile_library/trunk/rtl/verilog/defines.v
100 added cache mem with pipelined B4 behaviour unneback 4587d 00h /versatile_library/trunk/rtl/verilog/defines.v
98 work in progress unneback 4590d 23h /versatile_library/trunk/rtl/verilog/defines.v
97 cache is work in progress unneback 4592d 14h /versatile_library/trunk/rtl/verilog/defines.v
94 clock domain crossing unneback 4597d 15h /versatile_library/trunk/rtl/verilog/defines.v
92 wb b3 dpram with testcase unneback 4598d 00h /versatile_library/trunk/rtl/verilog/defines.v
83 new BE_RAM unneback 4601d 01h /versatile_library/trunk/rtl/verilog/defines.v
76 dependency for wb3 to avalon bus unneback 4605d 01h /versatile_library/trunk/rtl/verilog/defines.v
75 added wb to avalon bridge unneback 4605d 01h /versatile_library/trunk/rtl/verilog/defines.v
62 WB_B3_RAM_BE updates, bte port map + define dependency unneback 4651d 23h /versatile_library/trunk/rtl/verilog/defines.v
61 WB_B3_RAM_BE updates, bte port map + define dependency unneback 4651d 23h /versatile_library/trunk/rtl/verilog/defines.v
60 added wb b3 byte enable memory, added test in makefile through icarus, typo in latch fixed unneback 4653d 18h /versatile_library/trunk/rtl/verilog/defines.v
59 added WB RAM B3 with byte enable unneback 4654d 18h /versatile_library/trunk/rtl/verilog/defines.v
49 added WB_B4RAM with byte enable unneback 4686d 01h /versatile_library/trunk/rtl/verilog/defines.v
48 wb updated unneback 4692d 19h /versatile_library/trunk/rtl/verilog/defines.v
44 added target independet IO functionns unneback 4793d 18h /versatile_library/trunk/rtl/verilog/defines.v
43 added logic for parity generation and check unneback 4797d 21h /versatile_library/trunk/rtl/verilog/defines.v
42 updated mux_andor unneback 4801d 21h /versatile_library/trunk/rtl/verilog/defines.v
40 new build environment with custom.v added as a result file unneback 4801d 22h /versatile_library/trunk/rtl/verilog/defines.v

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