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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [defines.v] - Rev 54

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49 added WB_B4RAM with byte enable unneback 4687d 00h /versatile_library/trunk/rtl/verilog/defines.v
48 wb updated unneback 4693d 18h /versatile_library/trunk/rtl/verilog/defines.v
44 added target independet IO functionns unneback 4794d 16h /versatile_library/trunk/rtl/verilog/defines.v
43 added logic for parity generation and check unneback 4798d 20h /versatile_library/trunk/rtl/verilog/defines.v
42 updated mux_andor unneback 4802d 19h /versatile_library/trunk/rtl/verilog/defines.v
40 new build environment with custom.v added as a result file unneback 4802d 21h /versatile_library/trunk/rtl/verilog/defines.v

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