URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [defines.v] - Rev 60

Rev	Log message	Author	Age	Path
60	added wb b3 byte enable memory, added test in makefile through icarus, typo in latch fixed	unneback	4675d 13h	/versatile_library/trunk/rtl/verilog/defines.v
59	added WB RAM B3 with byte enable	unneback	4676d 13h	/versatile_library/trunk/rtl/verilog/defines.v
49	added WB_B4RAM with byte enable	unneback	4707d 20h	/versatile_library/trunk/rtl/verilog/defines.v
48	wb updated	unneback	4714d 14h	/versatile_library/trunk/rtl/verilog/defines.v
44	added target independet IO functionns	unneback	4815d 13h	/versatile_library/trunk/rtl/verilog/defines.v
43	added logic for parity generation and check	unneback	4819d 16h	/versatile_library/trunk/rtl/verilog/defines.v
42	updated mux_andor	unneback	4823d 16h	/versatile_library/trunk/rtl/verilog/defines.v
40	new build environment with custom.v added as a result file	unneback	4823d 17h	/versatile_library/trunk/rtl/verilog/defines.v