OpenCores
URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [defines.v] - Rev 61

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
61 WB_B3_RAM_BE updates, bte port map + define dependency unneback 4653d 04h /versatile_library/trunk/rtl/verilog/defines.v
60 added wb b3 byte enable memory, added test in makefile through icarus, typo in latch fixed unneback 4654d 23h /versatile_library/trunk/rtl/verilog/defines.v
59 added WB RAM B3 with byte enable unneback 4655d 23h /versatile_library/trunk/rtl/verilog/defines.v
49 added WB_B4RAM with byte enable unneback 4687d 06h /versatile_library/trunk/rtl/verilog/defines.v
48 wb updated unneback 4694d 00h /versatile_library/trunk/rtl/verilog/defines.v
44 added target independet IO functionns unneback 4794d 23h /versatile_library/trunk/rtl/verilog/defines.v
43 added logic for parity generation and check unneback 4799d 02h /versatile_library/trunk/rtl/verilog/defines.v
42 updated mux_andor unneback 4803d 02h /versatile_library/trunk/rtl/verilog/defines.v
40 new build environment with custom.v added as a result file unneback 4803d 03h /versatile_library/trunk/rtl/verilog/defines.v

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.