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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [defines.v] - Rev 75

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75 added wb to avalon bridge unneback 4492d 10h /versatile_library/trunk/rtl/verilog/defines.v
62 WB_B3_RAM_BE updates, bte port map + define dependency unneback 4539d 08h /versatile_library/trunk/rtl/verilog/defines.v
61 WB_B3_RAM_BE updates, bte port map + define dependency unneback 4539d 08h /versatile_library/trunk/rtl/verilog/defines.v
60 added wb b3 byte enable memory, added test in makefile through icarus, typo in latch fixed unneback 4541d 04h /versatile_library/trunk/rtl/verilog/defines.v
59 added WB RAM B3 with byte enable unneback 4542d 04h /versatile_library/trunk/rtl/verilog/defines.v
49 added WB_B4RAM with byte enable unneback 4573d 11h /versatile_library/trunk/rtl/verilog/defines.v
48 wb updated unneback 4580d 04h /versatile_library/trunk/rtl/verilog/defines.v
44 added target independet IO functionns unneback 4681d 03h /versatile_library/trunk/rtl/verilog/defines.v
43 added logic for parity generation and check unneback 4685d 06h /versatile_library/trunk/rtl/verilog/defines.v
42 updated mux_andor unneback 4689d 06h /versatile_library/trunk/rtl/verilog/defines.v
40 new build environment with custom.v added as a result file unneback 4689d 08h /versatile_library/trunk/rtl/verilog/defines.v

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