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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [defines.v] - Rev 75

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75 added wb to avalon bridge unneback 3392d 20h /versatile_library/trunk/rtl/verilog/defines.v
62 WB_B3_RAM_BE updates, bte port map + define dependency unneback 3439d 18h /versatile_library/trunk/rtl/verilog/defines.v
61 WB_B3_RAM_BE updates, bte port map + define dependency unneback 3439d 18h /versatile_library/trunk/rtl/verilog/defines.v
60 added wb b3 byte enable memory, added test in makefile through icarus, typo in latch fixed unneback 3441d 13h /versatile_library/trunk/rtl/verilog/defines.v
59 added WB RAM B3 with byte enable unneback 3442d 14h /versatile_library/trunk/rtl/verilog/defines.v
49 added WB_B4RAM with byte enable unneback 3473d 20h /versatile_library/trunk/rtl/verilog/defines.v
48 wb updated unneback 3480d 14h /versatile_library/trunk/rtl/verilog/defines.v
44 added target independet IO functionns unneback 3581d 13h /versatile_library/trunk/rtl/verilog/defines.v
43 added logic for parity generation and check unneback 3585d 16h /versatile_library/trunk/rtl/verilog/defines.v
42 updated mux_andor unneback 3589d 16h /versatile_library/trunk/rtl/verilog/defines.v
40 new build environment with custom.v added as a result file unneback 3589d 18h /versatile_library/trunk/rtl/verilog/defines.v

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