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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [defines.v] - Rev 95

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94 clock domain crossing unneback 4620d 15h /versatile_library/trunk/rtl/verilog/defines.v
92 wb b3 dpram with testcase unneback 4620d 23h /versatile_library/trunk/rtl/verilog/defines.v
83 new BE_RAM unneback 4624d 00h /versatile_library/trunk/rtl/verilog/defines.v
76 dependency for wb3 to avalon bus unneback 4628d 00h /versatile_library/trunk/rtl/verilog/defines.v
75 added wb to avalon bridge unneback 4628d 00h /versatile_library/trunk/rtl/verilog/defines.v
62 WB_B3_RAM_BE updates, bte port map + define dependency unneback 4674d 22h /versatile_library/trunk/rtl/verilog/defines.v
61 WB_B3_RAM_BE updates, bte port map + define dependency unneback 4674d 22h /versatile_library/trunk/rtl/verilog/defines.v
60 added wb b3 byte enable memory, added test in makefile through icarus, typo in latch fixed unneback 4676d 18h /versatile_library/trunk/rtl/verilog/defines.v
59 added WB RAM B3 with byte enable unneback 4677d 18h /versatile_library/trunk/rtl/verilog/defines.v
49 added WB_B4RAM with byte enable unneback 4709d 00h /versatile_library/trunk/rtl/verilog/defines.v
48 wb updated unneback 4715d 18h /versatile_library/trunk/rtl/verilog/defines.v
44 added target independet IO functionns unneback 4816d 17h /versatile_library/trunk/rtl/verilog/defines.v
43 added logic for parity generation and check unneback 4820d 20h /versatile_library/trunk/rtl/verilog/defines.v
42 updated mux_andor unneback 4824d 20h /versatile_library/trunk/rtl/verilog/defines.v
40 new build environment with custom.v added as a result file unneback 4824d 22h /versatile_library/trunk/rtl/verilog/defines.v

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