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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [memories.v] - Rev 111

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40 new build environment with custom.v added as a result file unneback 4997d 18h /versatile_library/trunk/rtl/verilog/memories.v
31 sync FIFO updated unneback 5046d 15h /versatile_library/trunk/rtl/verilog/memories.v
28 added sync simplex FIFO unneback 5047d 16h /versatile_library/trunk/rtl/verilog/memories.v
27 added sync simplex FIFO unneback 5047d 16h /versatile_library/trunk/rtl/verilog/memories.v
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 5047d 18h /versatile_library/trunk/rtl/verilog/memories.v
25 added sync FIFO unneback 5048d 07h /versatile_library/trunk/rtl/verilog/memories.v
23 fixed port map error in async fifo 1r1w unneback 5050d 05h /versatile_library/trunk/rtl/verilog/memories.v
21 reg -> wire in and or mux in logic unneback 5051d 07h /versatile_library/trunk/rtl/verilog/memories.v
18 naming convention vl_ unneback 5052d 18h /versatile_library/trunk/rtl/verilog/memories.v
14 reg -> wire for various signals unneback 5122d 20h /versatile_library/trunk/rtl/verilog/memories.v

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