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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [memories.v] - Rev 123

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60 added wb b3 byte enable memory, added test in makefile through icarus, typo in latch fixed unneback 4655d 00h /versatile_library/trunk/rtl/verilog/memories.v
48 wb updated unneback 4694d 00h /versatile_library/trunk/rtl/verilog/memories.v
40 new build environment with custom.v added as a result file unneback 4803d 04h /versatile_library/trunk/rtl/verilog/memories.v
31 sync FIFO updated unneback 4852d 00h /versatile_library/trunk/rtl/verilog/memories.v
28 added sync simplex FIFO unneback 4853d 02h /versatile_library/trunk/rtl/verilog/memories.v
27 added sync simplex FIFO unneback 4853d 02h /versatile_library/trunk/rtl/verilog/memories.v
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 4853d 03h /versatile_library/trunk/rtl/verilog/memories.v
25 added sync FIFO unneback 4853d 17h /versatile_library/trunk/rtl/verilog/memories.v
23 fixed port map error in async fifo 1r1w unneback 4855d 15h /versatile_library/trunk/rtl/verilog/memories.v
21 reg -> wire in and or mux in logic unneback 4856d 16h /versatile_library/trunk/rtl/verilog/memories.v

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