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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [memories.v] - Rev 128

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72 no arbiter in wb_b3_ram_be unneback 4613d 09h /versatile_library/trunk/rtl/verilog/memories.v
68 ram_be updated to optional mem_size unneback 4613d 09h /versatile_library/trunk/rtl/verilog/memories.v
65 RAM_BE system verilog version unneback 4652d 09h /versatile_library/trunk/rtl/verilog/memories.v
60 added wb b3 byte enable memory, added test in makefile through icarus, typo in latch fixed unneback 4654d 05h /versatile_library/trunk/rtl/verilog/memories.v
48 wb updated unneback 4693d 05h /versatile_library/trunk/rtl/verilog/memories.v
40 new build environment with custom.v added as a result file unneback 4802d 09h /versatile_library/trunk/rtl/verilog/memories.v
31 sync FIFO updated unneback 4851d 05h /versatile_library/trunk/rtl/verilog/memories.v
28 added sync simplex FIFO unneback 4852d 07h /versatile_library/trunk/rtl/verilog/memories.v
27 added sync simplex FIFO unneback 4852d 07h /versatile_library/trunk/rtl/verilog/memories.v
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 4852d 08h /versatile_library/trunk/rtl/verilog/memories.v

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