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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [memories.v] - Rev 14

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Rev Log message Author Age Path
14 reg -> wire for various signals unneback 3673d 03h /versatile_library/trunk/rtl/verilog/memories.v
11 async fifo simplex unneback 3674d 15h /versatile_library/trunk/rtl/verilog/memories.v
7 mem update unneback 3676d 15h /versatile_library/trunk/rtl/verilog/memories.v
5 memories added unneback 3689d 16h /versatile_library/trunk/rtl/verilog/memories.v

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