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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [memories.v] - Rev 23

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Rev Log message Author Age Path
23 fixed port map error in async fifo 1r1w unneback 4059d 20h /versatile_library/trunk/rtl/verilog/memories.v
21 reg -> wire in and or mux in logic unneback 4060d 21h /versatile_library/trunk/rtl/verilog/memories.v
18 naming convention vl_ unneback 4062d 08h /versatile_library/trunk/rtl/verilog/memories.v
14 reg -> wire for various signals unneback 4132d 10h /versatile_library/trunk/rtl/verilog/memories.v
11 async fifo simplex unneback 4133d 23h /versatile_library/trunk/rtl/verilog/memories.v
7 mem update unneback 4135d 23h /versatile_library/trunk/rtl/verilog/memories.v
5 memories added unneback 4149d 00h /versatile_library/trunk/rtl/verilog/memories.v

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