URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [memories.v] - Rev 23

Rev	Log message	Author	Age	Path
23	fixed port map error in async fifo 1r1w	unneback	4882d 12h	/versatile_library/trunk/rtl/verilog/memories.v
21	reg -> wire in and or mux in logic	unneback	4883d 13h	/versatile_library/trunk/rtl/verilog/memories.v
18	naming convention vl_	unneback	4885d 00h	/versatile_library/trunk/rtl/verilog/memories.v
14	reg -> wire for various signals	unneback	4955d 03h	/versatile_library/trunk/rtl/verilog/memories.v
11	async fifo simplex	unneback	4956d 15h	/versatile_library/trunk/rtl/verilog/memories.v
7	mem update	unneback	4958d 15h	/versatile_library/trunk/rtl/verilog/memories.v
5	memories added	unneback	4971d 16h	/versatile_library/trunk/rtl/verilog/memories.v