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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [memories.v] - Rev 26

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Rev Log message Author Age Path
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 3843d 23h /versatile_library/trunk/rtl/verilog/memories.v
25 added sync FIFO unneback 3844d 13h /versatile_library/trunk/rtl/verilog/memories.v
23 fixed port map error in async fifo 1r1w unneback 3846d 11h /versatile_library/trunk/rtl/verilog/memories.v
21 reg -> wire in and or mux in logic unneback 3847d 12h /versatile_library/trunk/rtl/verilog/memories.v
18 naming convention vl_ unneback 3848d 23h /versatile_library/trunk/rtl/verilog/memories.v
14 reg -> wire for various signals unneback 3919d 02h /versatile_library/trunk/rtl/verilog/memories.v
11 async fifo simplex unneback 3920d 14h /versatile_library/trunk/rtl/verilog/memories.v
7 mem update unneback 3922d 14h /versatile_library/trunk/rtl/verilog/memories.v
5 memories added unneback 3935d 15h /versatile_library/trunk/rtl/verilog/memories.v

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