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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [memories.v] - Rev 28

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Rev Log message Author Age Path
28 added sync simplex FIFO unneback 3842d 02h /versatile_library/trunk/rtl/verilog/memories.v
27 added sync simplex FIFO unneback 3842d 02h /versatile_library/trunk/rtl/verilog/memories.v
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 3842d 04h /versatile_library/trunk/rtl/verilog/memories.v
25 added sync FIFO unneback 3842d 17h /versatile_library/trunk/rtl/verilog/memories.v
23 fixed port map error in async fifo 1r1w unneback 3844d 16h /versatile_library/trunk/rtl/verilog/memories.v
21 reg -> wire in and or mux in logic unneback 3845d 17h /versatile_library/trunk/rtl/verilog/memories.v
18 naming convention vl_ unneback 3847d 04h /versatile_library/trunk/rtl/verilog/memories.v
14 reg -> wire for various signals unneback 3917d 06h /versatile_library/trunk/rtl/verilog/memories.v
11 async fifo simplex unneback 3918d 19h /versatile_library/trunk/rtl/verilog/memories.v
7 mem update unneback 3920d 19h /versatile_library/trunk/rtl/verilog/memories.v
5 memories added unneback 3933d 19h /versatile_library/trunk/rtl/verilog/memories.v

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