URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [memories.v] - Rev 31

Rev	Log message	Author	Age	Path
31	sync FIFO updated	unneback	4879d 07h	/versatile_library/trunk/rtl/verilog/memories.v
28	added sync simplex FIFO	unneback	4880d 09h	/versatile_library/trunk/rtl/verilog/memories.v
27	added sync simplex FIFO	unneback	4880d 09h	/versatile_library/trunk/rtl/verilog/memories.v
26	typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q	unneback	4880d 10h	/versatile_library/trunk/rtl/verilog/memories.v
25	added sync FIFO	unneback	4881d 00h	/versatile_library/trunk/rtl/verilog/memories.v
23	fixed port map error in async fifo 1r1w	unneback	4882d 22h	/versatile_library/trunk/rtl/verilog/memories.v
21	reg -> wire in and or mux in logic	unneback	4883d 23h	/versatile_library/trunk/rtl/verilog/memories.v
18	naming convention vl_	unneback	4885d 11h	/versatile_library/trunk/rtl/verilog/memories.v
14	reg -> wire for various signals	unneback	4955d 13h	/versatile_library/trunk/rtl/verilog/memories.v
11	async fifo simplex	unneback	4957d 01h	/versatile_library/trunk/rtl/verilog/memories.v
7	mem update	unneback	4959d 01h	/versatile_library/trunk/rtl/verilog/memories.v
5	memories added	unneback	4972d 02h	/versatile_library/trunk/rtl/verilog/memories.v