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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [memories.v] - Rev 31

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Rev Log message Author Age Path
31 sync FIFO updated unneback 5101d 05h /versatile_library/trunk/rtl/verilog/memories.v
28 added sync simplex FIFO unneback 5102d 06h /versatile_library/trunk/rtl/verilog/memories.v
27 added sync simplex FIFO unneback 5102d 06h /versatile_library/trunk/rtl/verilog/memories.v
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 5102d 07h /versatile_library/trunk/rtl/verilog/memories.v
25 added sync FIFO unneback 5102d 21h /versatile_library/trunk/rtl/verilog/memories.v
23 fixed port map error in async fifo 1r1w unneback 5104d 19h /versatile_library/trunk/rtl/verilog/memories.v
21 reg -> wire in and or mux in logic unneback 5105d 21h /versatile_library/trunk/rtl/verilog/memories.v
18 naming convention vl_ unneback 5107d 08h /versatile_library/trunk/rtl/verilog/memories.v
14 reg -> wire for various signals unneback 5177d 10h /versatile_library/trunk/rtl/verilog/memories.v
11 async fifo simplex unneback 5178d 22h /versatile_library/trunk/rtl/verilog/memories.v
7 mem update unneback 5180d 22h /versatile_library/trunk/rtl/verilog/memories.v
5 memories added unneback 5193d 23h /versatile_library/trunk/rtl/verilog/memories.v

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