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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [memories.v] - Rev 31

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Rev Log message Author Age Path
31 sync FIFO updated unneback 4431d 21h /versatile_library/trunk/rtl/verilog/memories.v
28 added sync simplex FIFO unneback 4432d 23h /versatile_library/trunk/rtl/verilog/memories.v
27 added sync simplex FIFO unneback 4432d 23h /versatile_library/trunk/rtl/verilog/memories.v
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 4433d 00h /versatile_library/trunk/rtl/verilog/memories.v
25 added sync FIFO unneback 4433d 13h /versatile_library/trunk/rtl/verilog/memories.v
23 fixed port map error in async fifo 1r1w unneback 4435d 12h /versatile_library/trunk/rtl/verilog/memories.v
21 reg -> wire in and or mux in logic unneback 4436d 13h /versatile_library/trunk/rtl/verilog/memories.v
18 naming convention vl_ unneback 4438d 00h /versatile_library/trunk/rtl/verilog/memories.v
14 reg -> wire for various signals unneback 4508d 02h /versatile_library/trunk/rtl/verilog/memories.v
11 async fifo simplex unneback 4509d 15h /versatile_library/trunk/rtl/verilog/memories.v
7 mem update unneback 4511d 15h /versatile_library/trunk/rtl/verilog/memories.v
5 memories added unneback 4524d 16h /versatile_library/trunk/rtl/verilog/memories.v

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