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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [memories.v] - Rev 73

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Rev Log message Author Age Path
73 no arbiter in wb_b3_ram_be unneback 4436d 10h /versatile_library/trunk/rtl/verilog/memories.v
72 no arbiter in wb_b3_ram_be unneback 4436d 10h /versatile_library/trunk/rtl/verilog/memories.v
68 ram_be updated to optional mem_size unneback 4436d 11h /versatile_library/trunk/rtl/verilog/memories.v
65 RAM_BE system verilog version unneback 4475d 10h /versatile_library/trunk/rtl/verilog/memories.v
60 added wb b3 byte enable memory, added test in makefile through icarus, typo in latch fixed unneback 4477d 06h /versatile_library/trunk/rtl/verilog/memories.v
48 wb updated unneback 4516d 07h /versatile_library/trunk/rtl/verilog/memories.v
40 new build environment with custom.v added as a result file unneback 4625d 10h /versatile_library/trunk/rtl/verilog/memories.v
31 sync FIFO updated unneback 4674d 07h /versatile_library/trunk/rtl/verilog/memories.v
28 added sync simplex FIFO unneback 4675d 08h /versatile_library/trunk/rtl/verilog/memories.v
27 added sync simplex FIFO unneback 4675d 08h /versatile_library/trunk/rtl/verilog/memories.v
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 4675d 10h /versatile_library/trunk/rtl/verilog/memories.v
25 added sync FIFO unneback 4675d 23h /versatile_library/trunk/rtl/verilog/memories.v
23 fixed port map error in async fifo 1r1w unneback 4677d 22h /versatile_library/trunk/rtl/verilog/memories.v
21 reg -> wire in and or mux in logic unneback 4678d 23h /versatile_library/trunk/rtl/verilog/memories.v
18 naming convention vl_ unneback 4680d 10h /versatile_library/trunk/rtl/verilog/memories.v
14 reg -> wire for various signals unneback 4750d 12h /versatile_library/trunk/rtl/verilog/memories.v
11 async fifo simplex unneback 4752d 01h /versatile_library/trunk/rtl/verilog/memories.v
7 mem update unneback 4754d 00h /versatile_library/trunk/rtl/verilog/memories.v
5 memories added unneback 4767d 01h /versatile_library/trunk/rtl/verilog/memories.v

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