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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [memories.v] - Rev 75

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Rev Log message Author Age Path
75 added wb to avalon bridge unneback 5023d 11h /versatile_library/trunk/rtl/verilog/memories.v
73 no arbiter in wb_b3_ram_be unneback 5031d 09h /versatile_library/trunk/rtl/verilog/memories.v
72 no arbiter in wb_b3_ram_be unneback 5031d 09h /versatile_library/trunk/rtl/verilog/memories.v
68 ram_be updated to optional mem_size unneback 5031d 09h /versatile_library/trunk/rtl/verilog/memories.v
65 RAM_BE system verilog version unneback 5070d 09h /versatile_library/trunk/rtl/verilog/memories.v
60 added wb b3 byte enable memory, added test in makefile through icarus, typo in latch fixed unneback 5072d 05h /versatile_library/trunk/rtl/verilog/memories.v
48 wb updated unneback 5111d 05h /versatile_library/trunk/rtl/verilog/memories.v
40 new build environment with custom.v added as a result file unneback 5220d 09h /versatile_library/trunk/rtl/verilog/memories.v
31 sync FIFO updated unneback 5269d 05h /versatile_library/trunk/rtl/verilog/memories.v
28 added sync simplex FIFO unneback 5270d 07h /versatile_library/trunk/rtl/verilog/memories.v
27 added sync simplex FIFO unneback 5270d 07h /versatile_library/trunk/rtl/verilog/memories.v
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 5270d 08h /versatile_library/trunk/rtl/verilog/memories.v
25 added sync FIFO unneback 5270d 22h /versatile_library/trunk/rtl/verilog/memories.v
23 fixed port map error in async fifo 1r1w unneback 5272d 20h /versatile_library/trunk/rtl/verilog/memories.v
21 reg -> wire in and or mux in logic unneback 5273d 22h /versatile_library/trunk/rtl/verilog/memories.v
18 naming convention vl_ unneback 5275d 09h /versatile_library/trunk/rtl/verilog/memories.v
14 reg -> wire for various signals unneback 5345d 11h /versatile_library/trunk/rtl/verilog/memories.v
11 async fifo simplex unneback 5346d 23h /versatile_library/trunk/rtl/verilog/memories.v
7 mem update unneback 5348d 23h /versatile_library/trunk/rtl/verilog/memories.v
5 memories added unneback 5362d 00h /versatile_library/trunk/rtl/verilog/memories.v

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