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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [memories.v] - Rev 83

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Rev Log message Author Age Path
83 new BE_RAM unneback 3320d 01h /versatile_library/trunk/rtl/verilog/memories.v
77 bridge update unneback 3323d 22h /versatile_library/trunk/rtl/verilog/memories.v
75 added wb to avalon bridge unneback 3324d 01h /versatile_library/trunk/rtl/verilog/memories.v
73 no arbiter in wb_b3_ram_be unneback 3331d 23h /versatile_library/trunk/rtl/verilog/memories.v
72 no arbiter in wb_b3_ram_be unneback 3331d 23h /versatile_library/trunk/rtl/verilog/memories.v
68 ram_be updated to optional mem_size unneback 3331d 23h /versatile_library/trunk/rtl/verilog/memories.v
65 RAM_BE system verilog version unneback 3370d 23h /versatile_library/trunk/rtl/verilog/memories.v
60 added wb b3 byte enable memory, added test in makefile through icarus, typo in latch fixed unneback 3372d 19h /versatile_library/trunk/rtl/verilog/memories.v
48 wb updated unneback 3411d 19h /versatile_library/trunk/rtl/verilog/memories.v
40 new build environment with custom.v added as a result file unneback 3520d 23h /versatile_library/trunk/rtl/verilog/memories.v
31 sync FIFO updated unneback 3569d 19h /versatile_library/trunk/rtl/verilog/memories.v
28 added sync simplex FIFO unneback 3570d 21h /versatile_library/trunk/rtl/verilog/memories.v
27 added sync simplex FIFO unneback 3570d 21h /versatile_library/trunk/rtl/verilog/memories.v
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 3570d 22h /versatile_library/trunk/rtl/verilog/memories.v
25 added sync FIFO unneback 3571d 12h /versatile_library/trunk/rtl/verilog/memories.v
23 fixed port map error in async fifo 1r1w unneback 3573d 10h /versatile_library/trunk/rtl/verilog/memories.v
21 reg -> wire in and or mux in logic unneback 3574d 12h /versatile_library/trunk/rtl/verilog/memories.v
18 naming convention vl_ unneback 3575d 23h /versatile_library/trunk/rtl/verilog/memories.v
14 reg -> wire for various signals unneback 3646d 01h /versatile_library/trunk/rtl/verilog/memories.v
11 async fifo simplex unneback 3647d 13h /versatile_library/trunk/rtl/verilog/memories.v

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