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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [memories.v] - Rev 86

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Rev Log message Author Age Path
18 naming convention vl_ unneback 4857d 20h /versatile_library/trunk/rtl/verilog/memories.v
14 reg -> wire for various signals unneback 4927d 23h /versatile_library/trunk/rtl/verilog/memories.v
11 async fifo simplex unneback 4929d 11h /versatile_library/trunk/rtl/verilog/memories.v
7 mem update unneback 4931d 11h /versatile_library/trunk/rtl/verilog/memories.v
5 memories added unneback 4944d 12h /versatile_library/trunk/rtl/verilog/memories.v

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