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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [registers.v] - Rev 120

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Rev Log message Author Age Path
116 syncronizer clock unneback 4600d 10h /versatile_library/trunk/rtl/verilog/registers.v
100 added cache mem with pipelined B4 behaviour unneback 4609d 11h /versatile_library/trunk/rtl/verilog/registers.v
98 work in progress unneback 4613d 10h /versatile_library/trunk/rtl/verilog/registers.v
97 cache is work in progress unneback 4615d 02h /versatile_library/trunk/rtl/verilog/registers.v
94 clock domain crossing unneback 4620d 03h /versatile_library/trunk/rtl/verilog/registers.v
75 added wb to avalon bridge unneback 4627d 12h /versatile_library/trunk/rtl/verilog/registers.v
64 SPR reset value unneback 4674d 10h /versatile_library/trunk/rtl/verilog/registers.v
60 added wb b3 byte enable memory, added test in makefile through icarus, typo in latch fixed unneback 4676d 06h /versatile_library/trunk/rtl/verilog/registers.v
48 wb updated unneback 4715d 06h /versatile_library/trunk/rtl/verilog/registers.v
41 typo in registers.v unneback 4824d 09h /versatile_library/trunk/rtl/verilog/registers.v
40 new build environment with custom.v added as a result file unneback 4824d 10h /versatile_library/trunk/rtl/verilog/registers.v
29 updated counter for level1 and level2 function unneback 4873d 07h /versatile_library/trunk/rtl/verilog/registers.v
24 added vl_dff_ce_set unneback 4876d 06h /versatile_library/trunk/rtl/verilog/registers.v
18 naming convention vl_ unneback 4879d 10h /versatile_library/trunk/rtl/verilog/registers.v
17 unneback 4942d 23h /versatile_library/trunk/rtl/verilog/registers.v
15 added delay line unneback 4949d 07h /versatile_library/trunk/rtl/verilog/registers.v
10 added dff_ce_clear unneback 4952d 23h /versatile_library/trunk/rtl/verilog/registers.v
8 added dff_ce_clear unneback 4952d 23h /versatile_library/trunk/rtl/verilog/registers.v
5 memories added unneback 4966d 01h /versatile_library/trunk/rtl/verilog/registers.v
3 various updates
counter added		 unneback 4973d 00h /versatile_library/trunk/rtl/verilog/registers.v

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