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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [registers.v] - Rev 124

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Rev Log message Author Age Path
116 syncronizer clock unneback 3412d 12h /versatile_library/trunk/rtl/verilog/registers.v
100 added cache mem with pipelined B4 behaviour unneback 3421d 13h /versatile_library/trunk/rtl/verilog/registers.v
98 work in progress unneback 3425d 12h /versatile_library/trunk/rtl/verilog/registers.v
97 cache is work in progress unneback 3427d 04h /versatile_library/trunk/rtl/verilog/registers.v
94 clock domain crossing unneback 3432d 05h /versatile_library/trunk/rtl/verilog/registers.v
75 added wb to avalon bridge unneback 3439d 14h /versatile_library/trunk/rtl/verilog/registers.v
64 SPR reset value unneback 3486d 12h /versatile_library/trunk/rtl/verilog/registers.v
60 added wb b3 byte enable memory, added test in makefile through icarus, typo in latch fixed unneback 3488d 08h /versatile_library/trunk/rtl/verilog/registers.v
48 wb updated unneback 3527d 08h /versatile_library/trunk/rtl/verilog/registers.v
41 typo in registers.v unneback 3636d 12h /versatile_library/trunk/rtl/verilog/registers.v
40 new build environment with custom.v added as a result file unneback 3636d 12h /versatile_library/trunk/rtl/verilog/registers.v
29 updated counter for level1 and level2 function unneback 3685d 09h /versatile_library/trunk/rtl/verilog/registers.v
24 added vl_dff_ce_set unneback 3688d 09h /versatile_library/trunk/rtl/verilog/registers.v
18 naming convention vl_ unneback 3691d 12h /versatile_library/trunk/rtl/verilog/registers.v
17 unneback 3755d 01h /versatile_library/trunk/rtl/verilog/registers.v
15 added delay line unneback 3761d 09h /versatile_library/trunk/rtl/verilog/registers.v
10 added dff_ce_clear unneback 3765d 01h /versatile_library/trunk/rtl/verilog/registers.v
8 added dff_ce_clear unneback 3765d 01h /versatile_library/trunk/rtl/verilog/registers.v
5 memories added unneback 3778d 03h /versatile_library/trunk/rtl/verilog/registers.v
3 various updates
counter added
unneback 3785d 02h /versatile_library/trunk/rtl/verilog/registers.v

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