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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [registers.v] - Rev 139

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139 unneback 3455d 23h /versatile_library/trunk/rtl/verilog/registers.v
116 syncronizer clock unneback 3523d 07h /versatile_library/trunk/rtl/verilog/registers.v
100 added cache mem with pipelined B4 behaviour unneback 3532d 08h /versatile_library/trunk/rtl/verilog/registers.v
98 work in progress unneback 3536d 06h /versatile_library/trunk/rtl/verilog/registers.v
97 cache is work in progress unneback 3537d 22h /versatile_library/trunk/rtl/verilog/registers.v
94 clock domain crossing unneback 3542d 23h /versatile_library/trunk/rtl/verilog/registers.v
75 added wb to avalon bridge unneback 3550d 09h /versatile_library/trunk/rtl/verilog/registers.v
64 SPR reset value unneback 3597d 06h /versatile_library/trunk/rtl/verilog/registers.v
60 added wb b3 byte enable memory, added test in makefile through icarus, typo in latch fixed unneback 3599d 02h /versatile_library/trunk/rtl/verilog/registers.v
48 wb updated unneback 3638d 03h /versatile_library/trunk/rtl/verilog/registers.v
41 typo in registers.v unneback 3747d 06h /versatile_library/trunk/rtl/verilog/registers.v
40 new build environment with custom.v added as a result file unneback 3747d 06h /versatile_library/trunk/rtl/verilog/registers.v
29 updated counter for level1 and level2 function unneback 3796d 03h /versatile_library/trunk/rtl/verilog/registers.v
24 added vl_dff_ce_set unneback 3799d 03h /versatile_library/trunk/rtl/verilog/registers.v
18 naming convention vl_ unneback 3802d 06h /versatile_library/trunk/rtl/verilog/registers.v
17 unneback 3865d 19h /versatile_library/trunk/rtl/verilog/registers.v
15 added delay line unneback 3872d 03h /versatile_library/trunk/rtl/verilog/registers.v
10 added dff_ce_clear unneback 3875d 20h /versatile_library/trunk/rtl/verilog/registers.v
8 added dff_ce_clear unneback 3875d 20h /versatile_library/trunk/rtl/verilog/registers.v
5 memories added unneback 3888d 22h /versatile_library/trunk/rtl/verilog/registers.v

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