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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [registers.v] - Rev 139

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139 unneback 4627d 02h /versatile_library/trunk/rtl/verilog/registers.v
116 syncronizer clock unneback 4694d 10h /versatile_library/trunk/rtl/verilog/registers.v
100 added cache mem with pipelined B4 behaviour unneback 4703d 11h /versatile_library/trunk/rtl/verilog/registers.v
98 work in progress unneback 4707d 10h /versatile_library/trunk/rtl/verilog/registers.v
97 cache is work in progress unneback 4709d 02h /versatile_library/trunk/rtl/verilog/registers.v
94 clock domain crossing unneback 4714d 03h /versatile_library/trunk/rtl/verilog/registers.v
75 added wb to avalon bridge unneback 4721d 12h /versatile_library/trunk/rtl/verilog/registers.v
64 SPR reset value unneback 4768d 10h /versatile_library/trunk/rtl/verilog/registers.v
60 added wb b3 byte enable memory, added test in makefile through icarus, typo in latch fixed unneback 4770d 06h /versatile_library/trunk/rtl/verilog/registers.v
48 wb updated unneback 4809d 07h /versatile_library/trunk/rtl/verilog/registers.v
41 typo in registers.v unneback 4918d 10h /versatile_library/trunk/rtl/verilog/registers.v
40 new build environment with custom.v added as a result file unneback 4918d 10h /versatile_library/trunk/rtl/verilog/registers.v
29 updated counter for level1 and level2 function unneback 4967d 07h /versatile_library/trunk/rtl/verilog/registers.v
24 added vl_dff_ce_set unneback 4970d 07h /versatile_library/trunk/rtl/verilog/registers.v
18 naming convention vl_ unneback 4973d 10h /versatile_library/trunk/rtl/verilog/registers.v
17 unneback 5036d 23h /versatile_library/trunk/rtl/verilog/registers.v
15 added delay line unneback 5043d 07h /versatile_library/trunk/rtl/verilog/registers.v
10 added dff_ce_clear unneback 5046d 23h /versatile_library/trunk/rtl/verilog/registers.v
8 added dff_ce_clear unneback 5047d 00h /versatile_library/trunk/rtl/verilog/registers.v
5 memories added unneback 5060d 01h /versatile_library/trunk/rtl/verilog/registers.v

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