OpenCores
URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [registers.v] - Rev 141

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
139 unneback 4533d 11h /versatile_library/trunk/rtl/verilog/registers.v
116 syncronizer clock unneback 4600d 19h /versatile_library/trunk/rtl/verilog/registers.v
100 added cache mem with pipelined B4 behaviour unneback 4609d 20h /versatile_library/trunk/rtl/verilog/registers.v
98 work in progress unneback 4613d 18h /versatile_library/trunk/rtl/verilog/registers.v
97 cache is work in progress unneback 4615d 10h /versatile_library/trunk/rtl/verilog/registers.v
94 clock domain crossing unneback 4620d 11h /versatile_library/trunk/rtl/verilog/registers.v
75 added wb to avalon bridge unneback 4627d 21h /versatile_library/trunk/rtl/verilog/registers.v
64 SPR reset value unneback 4674d 18h /versatile_library/trunk/rtl/verilog/registers.v
60 added wb b3 byte enable memory, added test in makefile through icarus, typo in latch fixed unneback 4676d 14h /versatile_library/trunk/rtl/verilog/registers.v
48 wb updated unneback 4715d 15h /versatile_library/trunk/rtl/verilog/registers.v
41 typo in registers.v unneback 4824d 18h /versatile_library/trunk/rtl/verilog/registers.v
40 new build environment with custom.v added as a result file unneback 4824d 18h /versatile_library/trunk/rtl/verilog/registers.v
29 updated counter for level1 and level2 function unneback 4873d 15h /versatile_library/trunk/rtl/verilog/registers.v
24 added vl_dff_ce_set unneback 4876d 15h /versatile_library/trunk/rtl/verilog/registers.v
18 naming convention vl_ unneback 4879d 18h /versatile_library/trunk/rtl/verilog/registers.v
17 unneback 4943d 08h /versatile_library/trunk/rtl/verilog/registers.v
15 added delay line unneback 4949d 15h /versatile_library/trunk/rtl/verilog/registers.v
10 added dff_ce_clear unneback 4953d 08h /versatile_library/trunk/rtl/verilog/registers.v
8 added dff_ce_clear unneback 4953d 08h /versatile_library/trunk/rtl/verilog/registers.v
5 memories added unneback 4966d 10h /versatile_library/trunk/rtl/verilog/registers.v

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.