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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [registers.v] - Rev 60

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60 added wb b3 byte enable memory, added test in makefile through icarus, typo in latch fixed unneback 4653d 19h /versatile_library/trunk/rtl/verilog/registers.v
48 wb updated unneback 4692d 19h /versatile_library/trunk/rtl/verilog/registers.v
41 typo in registers.v unneback 4801d 23h /versatile_library/trunk/rtl/verilog/registers.v
40 new build environment with custom.v added as a result file unneback 4801d 23h /versatile_library/trunk/rtl/verilog/registers.v
29 updated counter for level1 and level2 function unneback 4850d 20h /versatile_library/trunk/rtl/verilog/registers.v
24 added vl_dff_ce_set unneback 4853d 20h /versatile_library/trunk/rtl/verilog/registers.v
18 naming convention vl_ unneback 4856d 23h /versatile_library/trunk/rtl/verilog/registers.v
17 unneback 4920d 12h /versatile_library/trunk/rtl/verilog/registers.v
15 added delay line unneback 4926d 20h /versatile_library/trunk/rtl/verilog/registers.v
10 added dff_ce_clear unneback 4930d 12h /versatile_library/trunk/rtl/verilog/registers.v
8 added dff_ce_clear unneback 4930d 12h /versatile_library/trunk/rtl/verilog/registers.v
5 memories added unneback 4943d 14h /versatile_library/trunk/rtl/verilog/registers.v
3 various updates
counter added
unneback 4950d 13h /versatile_library/trunk/rtl/verilog/registers.v

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