OpenCores
URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [registers.v] - Rev 60

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
60 added wb b3 byte enable memory, added test in makefile through icarus, typo in latch fixed unneback 3808d 08h /versatile_library/trunk/rtl/verilog/registers.v
48 wb updated unneback 3847d 09h /versatile_library/trunk/rtl/verilog/registers.v
41 typo in registers.v unneback 3956d 12h /versatile_library/trunk/rtl/verilog/registers.v
40 new build environment with custom.v added as a result file unneback 3956d 13h /versatile_library/trunk/rtl/verilog/registers.v
29 updated counter for level1 and level2 function unneback 4005d 10h /versatile_library/trunk/rtl/verilog/registers.v
24 added vl_dff_ce_set unneback 4008d 09h /versatile_library/trunk/rtl/verilog/registers.v
18 naming convention vl_ unneback 4011d 13h /versatile_library/trunk/rtl/verilog/registers.v
17 unneback 4075d 02h /versatile_library/trunk/rtl/verilog/registers.v
15 added delay line unneback 4081d 10h /versatile_library/trunk/rtl/verilog/registers.v
10 added dff_ce_clear unneback 4085d 02h /versatile_library/trunk/rtl/verilog/registers.v
8 added dff_ce_clear unneback 4085d 02h /versatile_library/trunk/rtl/verilog/registers.v
5 memories added unneback 4098d 04h /versatile_library/trunk/rtl/verilog/registers.v
3 various updates
counter added
unneback 4105d 03h /versatile_library/trunk/rtl/verilog/registers.v

powered by: WebSVN 2.1.0

© copyright 1999-2021 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.