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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [registers.v] - Rev 72

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Rev Log message Author Age Path
64 SPR reset value unneback 3862d 10h /versatile_library/trunk/rtl/verilog/registers.v
60 added wb b3 byte enable memory, added test in makefile through icarus, typo in latch fixed unneback 3864d 06h /versatile_library/trunk/rtl/verilog/registers.v
48 wb updated unneback 3903d 07h /versatile_library/trunk/rtl/verilog/registers.v
41 typo in registers.v unneback 4012d 10h /versatile_library/trunk/rtl/verilog/registers.v
40 new build environment with custom.v added as a result file unneback 4012d 10h /versatile_library/trunk/rtl/verilog/registers.v
29 updated counter for level1 and level2 function unneback 4061d 07h /versatile_library/trunk/rtl/verilog/registers.v
24 added vl_dff_ce_set unneback 4064d 07h /versatile_library/trunk/rtl/verilog/registers.v
18 naming convention vl_ unneback 4067d 10h /versatile_library/trunk/rtl/verilog/registers.v
17 unneback 4130d 23h /versatile_library/trunk/rtl/verilog/registers.v
15 added delay line unneback 4137d 07h /versatile_library/trunk/rtl/verilog/registers.v
10 added dff_ce_clear unneback 4140d 23h /versatile_library/trunk/rtl/verilog/registers.v
8 added dff_ce_clear unneback 4141d 00h /versatile_library/trunk/rtl/verilog/registers.v
5 memories added unneback 4154d 01h /versatile_library/trunk/rtl/verilog/registers.v
3 various updates
counter added
unneback 4161d 00h /versatile_library/trunk/rtl/verilog/registers.v

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