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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Rev 22

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Rev Log message Author Age Path
22 added binary counters unneback 3801d 11h /versatile_library/trunk/rtl/verilog/versatile_library.v
21 reg -> wire in and or mux in logic unneback 3802d 08h /versatile_library/trunk/rtl/verilog/versatile_library.v
18 naming convention vl_ unneback 3803d 19h /versatile_library/trunk/rtl/verilog/versatile_library.v
17 unneback 3867d 08h /versatile_library/trunk/rtl/verilog/versatile_library.v
15 added delay line unneback 3873d 16h /versatile_library/trunk/rtl/verilog/versatile_library.v
14 reg -> wire for various signals unneback 3873d 21h /versatile_library/trunk/rtl/verilog/versatile_library.v
13 cosmetic update unneback 3873d 22h /versatile_library/trunk/rtl/verilog/versatile_library.v
12 added wishbone comliant modules unneback 3874d 18h /versatile_library/trunk/rtl/verilog/versatile_library.v
11 async fifo simplex unneback 3875d 09h /versatile_library/trunk/rtl/verilog/versatile_library.v
10 added dff_ce_clear unneback 3877d 08h /versatile_library/trunk/rtl/verilog/versatile_library.v
8 added dff_ce_clear unneback 3877d 08h /versatile_library/trunk/rtl/verilog/versatile_library.v
7 mem update unneback 3877d 09h /versatile_library/trunk/rtl/verilog/versatile_library.v
6 added library files unneback 3890d 10h /versatile_library/trunk/rtl/verilog/versatile_library.v

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