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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Rev 22

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Rev Log message Author Age Path
22 added binary counters unneback 3498d 19h /versatile_library/trunk/rtl/verilog/versatile_library.v
21 reg -> wire in and or mux in logic unneback 3499d 15h /versatile_library/trunk/rtl/verilog/versatile_library.v
18 naming convention vl_ unneback 3501d 03h /versatile_library/trunk/rtl/verilog/versatile_library.v
17 unneback 3564d 16h /versatile_library/trunk/rtl/verilog/versatile_library.v
15 added delay line unneback 3571d 00h /versatile_library/trunk/rtl/verilog/versatile_library.v
14 reg -> wire for various signals unneback 3571d 05h /versatile_library/trunk/rtl/verilog/versatile_library.v
13 cosmetic update unneback 3571d 06h /versatile_library/trunk/rtl/verilog/versatile_library.v
12 added wishbone comliant modules unneback 3572d 02h /versatile_library/trunk/rtl/verilog/versatile_library.v
11 async fifo simplex unneback 3572d 17h /versatile_library/trunk/rtl/verilog/versatile_library.v
10 added dff_ce_clear unneback 3574d 16h /versatile_library/trunk/rtl/verilog/versatile_library.v
8 added dff_ce_clear unneback 3574d 16h /versatile_library/trunk/rtl/verilog/versatile_library.v
7 mem update unneback 3574d 17h /versatile_library/trunk/rtl/verilog/versatile_library.v
6 added library files unneback 3587d 17h /versatile_library/trunk/rtl/verilog/versatile_library.v

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