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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Rev 31

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Rev Log message Author Age Path
31 sync FIFO updated unneback 3966d 19h /versatile_library/trunk/rtl/verilog/versatile_library.v
30 updated counter for level1 and level2 function unneback 3966d 19h /versatile_library/trunk/rtl/verilog/versatile_library.v
29 updated counter for level1 and level2 function unneback 3966d 19h /versatile_library/trunk/rtl/verilog/versatile_library.v
28 added sync simplex FIFO unneback 3967d 20h /versatile_library/trunk/rtl/verilog/versatile_library.v
27 added sync simplex FIFO unneback 3967d 20h /versatile_library/trunk/rtl/verilog/versatile_library.v
25 added sync FIFO unneback 3968d 11h /versatile_library/trunk/rtl/verilog/versatile_library.v
24 added vl_dff_ce_set unneback 3969d 19h /versatile_library/trunk/rtl/verilog/versatile_library.v
23 fixed port map error in async fifo 1r1w unneback 3970d 10h /versatile_library/trunk/rtl/verilog/versatile_library.v
22 added binary counters unneback 3970d 15h /versatile_library/trunk/rtl/verilog/versatile_library.v
21 reg -> wire in and or mux in logic unneback 3971d 11h /versatile_library/trunk/rtl/verilog/versatile_library.v
18 naming convention vl_ unneback 3972d 22h /versatile_library/trunk/rtl/verilog/versatile_library.v
17 unneback 4036d 11h /versatile_library/trunk/rtl/verilog/versatile_library.v
15 added delay line unneback 4042d 19h /versatile_library/trunk/rtl/verilog/versatile_library.v
14 reg -> wire for various signals unneback 4043d 00h /versatile_library/trunk/rtl/verilog/versatile_library.v
13 cosmetic update unneback 4043d 02h /versatile_library/trunk/rtl/verilog/versatile_library.v
12 added wishbone comliant modules unneback 4043d 22h /versatile_library/trunk/rtl/verilog/versatile_library.v
11 async fifo simplex unneback 4044d 13h /versatile_library/trunk/rtl/verilog/versatile_library.v
10 added dff_ce_clear unneback 4046d 12h /versatile_library/trunk/rtl/verilog/versatile_library.v
8 added dff_ce_clear unneback 4046d 12h /versatile_library/trunk/rtl/verilog/versatile_library.v
7 mem update unneback 4046d 13h /versatile_library/trunk/rtl/verilog/versatile_library.v

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