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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Rev 35

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35 added vl_mux2_andor and vl_mux3_andor localparam unneback 3526d 05h /versatile_library/trunk/rtl/verilog/versatile_library.v
34 added vl_mux2_andor and vl_mux3_andor unneback 3526d 05h /versatile_library/trunk/rtl/verilog/versatile_library.v
33 updated wb3wb3_bridge unneback 3539d 07h /versatile_library/trunk/rtl/verilog/versatile_library.v
32 added vl_pll for ALTERA (cycloneIII) unneback 3546d 17h /versatile_library/trunk/rtl/verilog/versatile_library.v
31 sync FIFO updated unneback 3566d 12h /versatile_library/trunk/rtl/verilog/versatile_library.v
30 updated counter for level1 and level2 function unneback 3566d 12h /versatile_library/trunk/rtl/verilog/versatile_library.v
29 updated counter for level1 and level2 function unneback 3566d 13h /versatile_library/trunk/rtl/verilog/versatile_library.v
28 added sync simplex FIFO unneback 3567d 14h /versatile_library/trunk/rtl/verilog/versatile_library.v
27 added sync simplex FIFO unneback 3567d 14h /versatile_library/trunk/rtl/verilog/versatile_library.v
25 added sync FIFO unneback 3568d 05h /versatile_library/trunk/rtl/verilog/versatile_library.v
24 added vl_dff_ce_set unneback 3569d 12h /versatile_library/trunk/rtl/verilog/versatile_library.v
23 fixed port map error in async fifo 1r1w unneback 3570d 03h /versatile_library/trunk/rtl/verilog/versatile_library.v
22 added binary counters unneback 3570d 08h /versatile_library/trunk/rtl/verilog/versatile_library.v
21 reg -> wire in and or mux in logic unneback 3571d 04h /versatile_library/trunk/rtl/verilog/versatile_library.v
18 naming convention vl_ unneback 3572d 15h /versatile_library/trunk/rtl/verilog/versatile_library.v
17 unneback 3636d 05h /versatile_library/trunk/rtl/verilog/versatile_library.v
15 added delay line unneback 3642d 13h /versatile_library/trunk/rtl/verilog/versatile_library.v
14 reg -> wire for various signals unneback 3642d 18h /versatile_library/trunk/rtl/verilog/versatile_library.v
13 cosmetic update unneback 3642d 19h /versatile_library/trunk/rtl/verilog/versatile_library.v
12 added wishbone comliant modules unneback 3643d 15h /versatile_library/trunk/rtl/verilog/versatile_library.v
11 async fifo simplex unneback 3644d 06h /versatile_library/trunk/rtl/verilog/versatile_library.v
10 added dff_ce_clear unneback 3646d 05h /versatile_library/trunk/rtl/verilog/versatile_library.v
8 added dff_ce_clear unneback 3646d 05h /versatile_library/trunk/rtl/verilog/versatile_library.v
7 mem update unneback 3646d 06h /versatile_library/trunk/rtl/verilog/versatile_library.v
6 added library files unneback 3659d 06h /versatile_library/trunk/rtl/verilog/versatile_library.v

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