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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Rev 37

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Rev Log message Author Age Path
37 corrected polynom with length 20 unneback 4331d 07h /versatile_library/trunk/rtl/verilog/versatile_library.v
36 added generic andor_mux unneback 4332d 16h /versatile_library/trunk/rtl/verilog/versatile_library.v
35 added vl_mux2_andor and vl_mux3_andor localparam unneback 4333d 03h /versatile_library/trunk/rtl/verilog/versatile_library.v
34 added vl_mux2_andor and vl_mux3_andor unneback 4333d 03h /versatile_library/trunk/rtl/verilog/versatile_library.v
33 updated wb3wb3_bridge unneback 4346d 05h /versatile_library/trunk/rtl/verilog/versatile_library.v
32 added vl_pll for ALTERA (cycloneIII) unneback 4353d 15h /versatile_library/trunk/rtl/verilog/versatile_library.v
31 sync FIFO updated unneback 4373d 10h /versatile_library/trunk/rtl/verilog/versatile_library.v
30 updated counter for level1 and level2 function unneback 4373d 11h /versatile_library/trunk/rtl/verilog/versatile_library.v
29 updated counter for level1 and level2 function unneback 4373d 11h /versatile_library/trunk/rtl/verilog/versatile_library.v
28 added sync simplex FIFO unneback 4374d 12h /versatile_library/trunk/rtl/verilog/versatile_library.v
27 added sync simplex FIFO unneback 4374d 12h /versatile_library/trunk/rtl/verilog/versatile_library.v
25 added sync FIFO unneback 4375d 03h /versatile_library/trunk/rtl/verilog/versatile_library.v
24 added vl_dff_ce_set unneback 4376d 11h /versatile_library/trunk/rtl/verilog/versatile_library.v
23 fixed port map error in async fifo 1r1w unneback 4377d 01h /versatile_library/trunk/rtl/verilog/versatile_library.v
22 added binary counters unneback 4377d 06h /versatile_library/trunk/rtl/verilog/versatile_library.v
21 reg -> wire in and or mux in logic unneback 4378d 03h /versatile_library/trunk/rtl/verilog/versatile_library.v
18 naming convention vl_ unneback 4379d 14h /versatile_library/trunk/rtl/verilog/versatile_library.v
17 unneback 4443d 03h /versatile_library/trunk/rtl/verilog/versatile_library.v
15 added delay line unneback 4449d 11h /versatile_library/trunk/rtl/verilog/versatile_library.v
14 reg -> wire for various signals unneback 4449d 16h /versatile_library/trunk/rtl/verilog/versatile_library.v

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