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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Rev 37

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Rev Log message Author Age Path
37 corrected polynom with length 20 unneback 4808d 19h /versatile_library/trunk/rtl/verilog/versatile_library.v
36 added generic andor_mux unneback 4810d 03h /versatile_library/trunk/rtl/verilog/versatile_library.v
35 added vl_mux2_andor and vl_mux3_andor localparam unneback 4810d 15h /versatile_library/trunk/rtl/verilog/versatile_library.v
34 added vl_mux2_andor and vl_mux3_andor unneback 4810d 15h /versatile_library/trunk/rtl/verilog/versatile_library.v
33 updated wb3wb3_bridge unneback 4823d 17h /versatile_library/trunk/rtl/verilog/versatile_library.v
32 added vl_pll for ALTERA (cycloneIII) unneback 4831d 02h /versatile_library/trunk/rtl/verilog/versatile_library.v
31 sync FIFO updated unneback 4850d 22h /versatile_library/trunk/rtl/verilog/versatile_library.v
30 updated counter for level1 and level2 function unneback 4850d 22h /versatile_library/trunk/rtl/verilog/versatile_library.v
29 updated counter for level1 and level2 function unneback 4850d 22h /versatile_library/trunk/rtl/verilog/versatile_library.v
28 added sync simplex FIFO unneback 4852d 00h /versatile_library/trunk/rtl/verilog/versatile_library.v
27 added sync simplex FIFO unneback 4852d 00h /versatile_library/trunk/rtl/verilog/versatile_library.v
25 added sync FIFO unneback 4852d 14h /versatile_library/trunk/rtl/verilog/versatile_library.v
24 added vl_dff_ce_set unneback 4853d 22h /versatile_library/trunk/rtl/verilog/versatile_library.v
23 fixed port map error in async fifo 1r1w unneback 4854d 13h /versatile_library/trunk/rtl/verilog/versatile_library.v
22 added binary counters unneback 4854d 18h /versatile_library/trunk/rtl/verilog/versatile_library.v
21 reg -> wire in and or mux in logic unneback 4855d 14h /versatile_library/trunk/rtl/verilog/versatile_library.v
18 naming convention vl_ unneback 4857d 01h /versatile_library/trunk/rtl/verilog/versatile_library.v
17 unneback 4920d 15h /versatile_library/trunk/rtl/verilog/versatile_library.v
15 added delay line unneback 4926d 22h /versatile_library/trunk/rtl/verilog/versatile_library.v
14 reg -> wire for various signals unneback 4927d 04h /versatile_library/trunk/rtl/verilog/versatile_library.v
13 cosmetic update unneback 4927d 05h /versatile_library/trunk/rtl/verilog/versatile_library.v
12 added wishbone comliant modules unneback 4928d 01h /versatile_library/trunk/rtl/verilog/versatile_library.v
11 async fifo simplex unneback 4928d 16h /versatile_library/trunk/rtl/verilog/versatile_library.v
10 added dff_ce_clear unneback 4930d 15h /versatile_library/trunk/rtl/verilog/versatile_library.v
8 added dff_ce_clear unneback 4930d 15h /versatile_library/trunk/rtl/verilog/versatile_library.v
7 mem update unneback 4930d 16h /versatile_library/trunk/rtl/verilog/versatile_library.v
6 added library files unneback 4943d 16h /versatile_library/trunk/rtl/verilog/versatile_library.v

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