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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Rev 40

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40 new build environment with custom.v added as a result file unneback 4802d 00h /versatile_library/trunk/rtl/verilog/versatile_library.v
39 added simple port prio based wb arbiter unneback 4802d 21h /versatile_library/trunk/rtl/verilog/versatile_library.v
38 updated andor mux unneback 4802d 21h /versatile_library/trunk/rtl/verilog/versatile_library.v
37 corrected polynom with length 20 unneback 4808d 18h /versatile_library/trunk/rtl/verilog/versatile_library.v
36 added generic andor_mux unneback 4810d 02h /versatile_library/trunk/rtl/verilog/versatile_library.v
35 added vl_mux2_andor and vl_mux3_andor localparam unneback 4810d 13h /versatile_library/trunk/rtl/verilog/versatile_library.v
34 added vl_mux2_andor and vl_mux3_andor unneback 4810d 13h /versatile_library/trunk/rtl/verilog/versatile_library.v
33 updated wb3wb3_bridge unneback 4823d 15h /versatile_library/trunk/rtl/verilog/versatile_library.v
32 added vl_pll for ALTERA (cycloneIII) unneback 4831d 01h /versatile_library/trunk/rtl/verilog/versatile_library.v
31 sync FIFO updated unneback 4850d 21h /versatile_library/trunk/rtl/verilog/versatile_library.v
30 updated counter for level1 and level2 function unneback 4850d 21h /versatile_library/trunk/rtl/verilog/versatile_library.v
29 updated counter for level1 and level2 function unneback 4850d 21h /versatile_library/trunk/rtl/verilog/versatile_library.v
28 added sync simplex FIFO unneback 4851d 22h /versatile_library/trunk/rtl/verilog/versatile_library.v
27 added sync simplex FIFO unneback 4851d 23h /versatile_library/trunk/rtl/verilog/versatile_library.v
25 added sync FIFO unneback 4852d 13h /versatile_library/trunk/rtl/verilog/versatile_library.v
24 added vl_dff_ce_set unneback 4853d 21h /versatile_library/trunk/rtl/verilog/versatile_library.v
23 fixed port map error in async fifo 1r1w unneback 4854d 12h /versatile_library/trunk/rtl/verilog/versatile_library.v
22 added binary counters unneback 4854d 17h /versatile_library/trunk/rtl/verilog/versatile_library.v
21 reg -> wire in and or mux in logic unneback 4855d 13h /versatile_library/trunk/rtl/verilog/versatile_library.v
18 naming convention vl_ unneback 4857d 00h /versatile_library/trunk/rtl/verilog/versatile_library.v

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