URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Rev 42

Rev	Log message	Author	Age	Path
21	reg -> wire in and or mux in logic	unneback	5146d 10h	/versatile_library/trunk/rtl/verilog/versatile_library.v
18	naming convention vl_	unneback	5147d 21h	/versatile_library/trunk/rtl/verilog/versatile_library.v
17		unneback	5211d 11h	/versatile_library/trunk/rtl/verilog/versatile_library.v
15	added delay line	unneback	5217d 18h	/versatile_library/trunk/rtl/verilog/versatile_library.v
14	reg -> wire for various signals	unneback	5218d 00h	/versatile_library/trunk/rtl/verilog/versatile_library.v
13	cosmetic update	unneback	5218d 01h	/versatile_library/trunk/rtl/verilog/versatile_library.v
12	added wishbone comliant modules	unneback	5218d 21h	/versatile_library/trunk/rtl/verilog/versatile_library.v
11	async fifo simplex	unneback	5219d 12h	/versatile_library/trunk/rtl/verilog/versatile_library.v
10	added dff_ce_clear	unneback	5221d 11h	/versatile_library/trunk/rtl/verilog/versatile_library.v
8	added dff_ce_clear	unneback	5221d 11h	/versatile_library/trunk/rtl/verilog/versatile_library.v