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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Rev 43

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43 added logic for parity generation and check unneback 3223d 05h /versatile_library/trunk/rtl/verilog/versatile_library.v
42 updated mux_andor unneback 3227d 04h /versatile_library/trunk/rtl/verilog/versatile_library.v
41 typo in registers.v unneback 3227d 06h /versatile_library/trunk/rtl/verilog/versatile_library.v
40 new build environment with custom.v added as a result file unneback 3227d 06h /versatile_library/trunk/rtl/verilog/versatile_library.v
39 added simple port prio based wb arbiter unneback 3228d 03h /versatile_library/trunk/rtl/verilog/versatile_library.v
38 updated andor mux unneback 3228d 03h /versatile_library/trunk/rtl/verilog/versatile_library.v
37 corrected polynom with length 20 unneback 3234d 00h /versatile_library/trunk/rtl/verilog/versatile_library.v
36 added generic andor_mux unneback 3235d 08h /versatile_library/trunk/rtl/verilog/versatile_library.v
35 added vl_mux2_andor and vl_mux3_andor localparam unneback 3235d 19h /versatile_library/trunk/rtl/verilog/versatile_library.v
34 added vl_mux2_andor and vl_mux3_andor unneback 3235d 19h /versatile_library/trunk/rtl/verilog/versatile_library.v
33 updated wb3wb3_bridge unneback 3248d 21h /versatile_library/trunk/rtl/verilog/versatile_library.v
32 added vl_pll for ALTERA (cycloneIII) unneback 3256d 07h /versatile_library/trunk/rtl/verilog/versatile_library.v
31 sync FIFO updated unneback 3276d 03h /versatile_library/trunk/rtl/verilog/versatile_library.v
30 updated counter for level1 and level2 function unneback 3276d 03h /versatile_library/trunk/rtl/verilog/versatile_library.v
29 updated counter for level1 and level2 function unneback 3276d 03h /versatile_library/trunk/rtl/verilog/versatile_library.v
28 added sync simplex FIFO unneback 3277d 04h /versatile_library/trunk/rtl/verilog/versatile_library.v
27 added sync simplex FIFO unneback 3277d 04h /versatile_library/trunk/rtl/verilog/versatile_library.v
25 added sync FIFO unneback 3277d 19h /versatile_library/trunk/rtl/verilog/versatile_library.v
24 added vl_dff_ce_set unneback 3279d 03h /versatile_library/trunk/rtl/verilog/versatile_library.v
23 fixed port map error in async fifo 1r1w unneback 3279d 18h /versatile_library/trunk/rtl/verilog/versatile_library.v

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