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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Rev 51

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51 added WB_B4RAM with byte enable unneback 4014d 00h /versatile_library/trunk/rtl/verilog/versatile_library.v
50 added WB_B4RAM with byte enable unneback 4014d 00h /versatile_library/trunk/rtl/verilog/versatile_library.v
49 added WB_B4RAM with byte enable unneback 4014d 01h /versatile_library/trunk/rtl/verilog/versatile_library.v
48 wb updated unneback 4020d 18h /versatile_library/trunk/rtl/verilog/versatile_library.v
46 updated parity unneback 4116d 23h /versatile_library/trunk/rtl/verilog/versatile_library.v
45 updated timing in io models unneback 4118d 17h /versatile_library/trunk/rtl/verilog/versatile_library.v
44 added target independet IO functionns unneback 4121d 17h /versatile_library/trunk/rtl/verilog/versatile_library.v
43 added logic for parity generation and check unneback 4125d 20h /versatile_library/trunk/rtl/verilog/versatile_library.v
42 updated mux_andor unneback 4129d 20h /versatile_library/trunk/rtl/verilog/versatile_library.v
41 typo in registers.v unneback 4129d 22h /versatile_library/trunk/rtl/verilog/versatile_library.v
40 new build environment with custom.v added as a result file unneback 4129d 22h /versatile_library/trunk/rtl/verilog/versatile_library.v
39 added simple port prio based wb arbiter unneback 4130d 19h /versatile_library/trunk/rtl/verilog/versatile_library.v
38 updated andor mux unneback 4130d 19h /versatile_library/trunk/rtl/verilog/versatile_library.v
37 corrected polynom with length 20 unneback 4136d 15h /versatile_library/trunk/rtl/verilog/versatile_library.v
36 added generic andor_mux unneback 4138d 00h /versatile_library/trunk/rtl/verilog/versatile_library.v
35 added vl_mux2_andor and vl_mux3_andor localparam unneback 4138d 11h /versatile_library/trunk/rtl/verilog/versatile_library.v
34 added vl_mux2_andor and vl_mux3_andor unneback 4138d 11h /versatile_library/trunk/rtl/verilog/versatile_library.v
33 updated wb3wb3_bridge unneback 4151d 13h /versatile_library/trunk/rtl/verilog/versatile_library.v
32 added vl_pll for ALTERA (cycloneIII) unneback 4158d 23h /versatile_library/trunk/rtl/verilog/versatile_library.v
31 sync FIFO updated unneback 4178d 18h /versatile_library/trunk/rtl/verilog/versatile_library.v

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