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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Rev 51

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30 updated counter for level1 and level2 function unneback 4871d 17h /versatile_library/trunk/rtl/verilog/versatile_library.v
29 updated counter for level1 and level2 function unneback 4871d 17h /versatile_library/trunk/rtl/verilog/versatile_library.v
28 added sync simplex FIFO unneback 4872d 18h /versatile_library/trunk/rtl/verilog/versatile_library.v
27 added sync simplex FIFO unneback 4872d 18h /versatile_library/trunk/rtl/verilog/versatile_library.v
25 added sync FIFO unneback 4873d 09h /versatile_library/trunk/rtl/verilog/versatile_library.v
24 added vl_dff_ce_set unneback 4874d 17h /versatile_library/trunk/rtl/verilog/versatile_library.v
23 fixed port map error in async fifo 1r1w unneback 4875d 07h /versatile_library/trunk/rtl/verilog/versatile_library.v
22 added binary counters unneback 4875d 13h /versatile_library/trunk/rtl/verilog/versatile_library.v
21 reg -> wire in and or mux in logic unneback 4876d 09h /versatile_library/trunk/rtl/verilog/versatile_library.v
18 naming convention vl_ unneback 4877d 20h /versatile_library/trunk/rtl/verilog/versatile_library.v

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