OpenCores
URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Rev 53

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
53 added WB_B4RAM with byte enable unneback 4708d 15h /versatile_library/trunk/rtl/verilog/versatile_library.v
52 added WB_B4RAM with byte enable unneback 4708d 15h /versatile_library/trunk/rtl/verilog/versatile_library.v
51 added WB_B4RAM with byte enable unneback 4708d 15h /versatile_library/trunk/rtl/verilog/versatile_library.v
50 added WB_B4RAM with byte enable unneback 4708d 15h /versatile_library/trunk/rtl/verilog/versatile_library.v
49 added WB_B4RAM with byte enable unneback 4708d 15h /versatile_library/trunk/rtl/verilog/versatile_library.v
48 wb updated unneback 4715d 09h /versatile_library/trunk/rtl/verilog/versatile_library.v
46 updated parity unneback 4811d 14h /versatile_library/trunk/rtl/verilog/versatile_library.v
45 updated timing in io models unneback 4813d 08h /versatile_library/trunk/rtl/verilog/versatile_library.v
44 added target independet IO functionns unneback 4816d 08h /versatile_library/trunk/rtl/verilog/versatile_library.v
43 added logic for parity generation and check unneback 4820d 11h /versatile_library/trunk/rtl/verilog/versatile_library.v
42 updated mux_andor unneback 4824d 11h /versatile_library/trunk/rtl/verilog/versatile_library.v
41 typo in registers.v unneback 4824d 12h /versatile_library/trunk/rtl/verilog/versatile_library.v
40 new build environment with custom.v added as a result file unneback 4824d 12h /versatile_library/trunk/rtl/verilog/versatile_library.v
39 added simple port prio based wb arbiter unneback 4825d 09h /versatile_library/trunk/rtl/verilog/versatile_library.v
38 updated andor mux unneback 4825d 09h /versatile_library/trunk/rtl/verilog/versatile_library.v
37 corrected polynom with length 20 unneback 4831d 06h /versatile_library/trunk/rtl/verilog/versatile_library.v
36 added generic andor_mux unneback 4832d 14h /versatile_library/trunk/rtl/verilog/versatile_library.v
35 added vl_mux2_andor and vl_mux3_andor localparam unneback 4833d 02h /versatile_library/trunk/rtl/verilog/versatile_library.v
34 added vl_mux2_andor and vl_mux3_andor unneback 4833d 02h /versatile_library/trunk/rtl/verilog/versatile_library.v
33 updated wb3wb3_bridge unneback 4846d 04h /versatile_library/trunk/rtl/verilog/versatile_library.v
32 added vl_pll for ALTERA (cycloneIII) unneback 4853d 14h /versatile_library/trunk/rtl/verilog/versatile_library.v
31 sync FIFO updated unneback 4873d 09h /versatile_library/trunk/rtl/verilog/versatile_library.v
30 updated counter for level1 and level2 function unneback 4873d 09h /versatile_library/trunk/rtl/verilog/versatile_library.v
29 updated counter for level1 and level2 function unneback 4873d 09h /versatile_library/trunk/rtl/verilog/versatile_library.v
28 added sync simplex FIFO unneback 4874d 11h /versatile_library/trunk/rtl/verilog/versatile_library.v
27 added sync simplex FIFO unneback 4874d 11h /versatile_library/trunk/rtl/verilog/versatile_library.v
25 added sync FIFO unneback 4875d 02h /versatile_library/trunk/rtl/verilog/versatile_library.v
24 added vl_dff_ce_set unneback 4876d 09h /versatile_library/trunk/rtl/verilog/versatile_library.v
23 fixed port map error in async fifo 1r1w unneback 4877d 00h /versatile_library/trunk/rtl/verilog/versatile_library.v
22 added binary counters unneback 4877d 05h /versatile_library/trunk/rtl/verilog/versatile_library.v

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.