URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Rev 69

Rev	Log message	Author	Age	Path
49	added WB_B4RAM with byte enable	unneback	4708d 12h	/versatile_library/trunk/rtl/verilog/versatile_library.v
48	wb updated	unneback	4715d 06h	/versatile_library/trunk/rtl/verilog/versatile_library.v
46	updated parity	unneback	4811d 11h	/versatile_library/trunk/rtl/verilog/versatile_library.v
45	updated timing in io models	unneback	4813d 05h	/versatile_library/trunk/rtl/verilog/versatile_library.v
44	added target independet IO functionns	unneback	4816d 05h	/versatile_library/trunk/rtl/verilog/versatile_library.v
43	added logic for parity generation and check	unneback	4820d 08h	/versatile_library/trunk/rtl/verilog/versatile_library.v
42	updated mux_andor	unneback	4824d 08h	/versatile_library/trunk/rtl/verilog/versatile_library.v
41	typo in registers.v	unneback	4824d 09h	/versatile_library/trunk/rtl/verilog/versatile_library.v
40	new build environment with custom.v added as a result file	unneback	4824d 09h	/versatile_library/trunk/rtl/verilog/versatile_library.v
39	added simple port prio based wb arbiter	unneback	4825d 06h	/versatile_library/trunk/rtl/verilog/versatile_library.v