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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Rev 71

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51 added WB_B4RAM with byte enable unneback 4936d 15h /versatile_library/trunk/rtl/verilog/versatile_library.v
50 added WB_B4RAM with byte enable unneback 4936d 15h /versatile_library/trunk/rtl/verilog/versatile_library.v
49 added WB_B4RAM with byte enable unneback 4936d 16h /versatile_library/trunk/rtl/verilog/versatile_library.v
48 wb updated unneback 4943d 09h /versatile_library/trunk/rtl/verilog/versatile_library.v
46 updated parity unneback 5039d 14h /versatile_library/trunk/rtl/verilog/versatile_library.v
45 updated timing in io models unneback 5041d 08h /versatile_library/trunk/rtl/verilog/versatile_library.v
44 added target independet IO functionns unneback 5044d 08h /versatile_library/trunk/rtl/verilog/versatile_library.v
43 added logic for parity generation and check unneback 5048d 11h /versatile_library/trunk/rtl/verilog/versatile_library.v
42 updated mux_andor unneback 5052d 11h /versatile_library/trunk/rtl/verilog/versatile_library.v
41 typo in registers.v unneback 5052d 13h /versatile_library/trunk/rtl/verilog/versatile_library.v

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