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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_actel.v] - Rev 15

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Rev Log message Author Age Path
15 added delay line unneback 3398d 08h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
14 reg -> wire for various signals unneback 3398d 13h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
13 cosmetic update unneback 3398d 14h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
12 added wishbone comliant modules unneback 3399d 10h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
11 async fifo simplex unneback 3400d 01h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
10 added dff_ce_clear unneback 3402d 00h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
8 added dff_ce_clear unneback 3402d 00h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
7 mem update unneback 3402d 01h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
6 added library files unneback 3415d 01h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v

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