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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_actel.v] - Rev 24

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Rev Log message Author Age Path
24 added vl_dff_ce_set unneback 3933d 04h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
23 fixed port map error in async fifo 1r1w unneback 3933d 19h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
22 added binary counters unneback 3934d 00h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
21 reg -> wire in and or mux in logic unneback 3934d 20h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
18 naming convention vl_ unneback 3936d 07h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
17 unneback 3999d 20h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
15 added delay line unneback 4006d 04h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
14 reg -> wire for various signals unneback 4006d 09h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
13 cosmetic update unneback 4006d 11h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
12 added wishbone comliant modules unneback 4007d 07h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
11 async fifo simplex unneback 4007d 22h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
10 added dff_ce_clear unneback 4009d 21h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
8 added dff_ce_clear unneback 4009d 21h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
7 mem update unneback 4009d 22h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
6 added library files unneback 4022d 22h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v

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