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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_actel.v] - Rev 37

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Rev Log message Author Age Path
37 corrected polynom with length 20 unneback 4328d 16h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
36 added generic andor_mux unneback 4330d 01h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
35 added vl_mux2_andor and vl_mux3_andor localparam unneback 4330d 12h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
34 added vl_mux2_andor and vl_mux3_andor unneback 4330d 12h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
33 updated wb3wb3_bridge unneback 4343d 14h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
32 added vl_pll for ALTERA (cycloneIII) unneback 4351d 00h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
31 sync FIFO updated unneback 4370d 19h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
30 updated counter for level1 and level2 function unneback 4370d 20h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
29 updated counter for level1 and level2 function unneback 4370d 20h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
28 added sync simplex FIFO unneback 4371d 21h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
27 added sync simplex FIFO unneback 4371d 21h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
25 added sync FIFO unneback 4372d 12h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
24 added vl_dff_ce_set unneback 4373d 20h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
23 fixed port map error in async fifo 1r1w unneback 4374d 10h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
22 added binary counters unneback 4374d 15h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
21 reg -> wire in and or mux in logic unneback 4375d 12h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
18 naming convention vl_ unneback 4376d 23h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
17 unneback 4440d 12h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
15 added delay line unneback 4446d 20h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
14 reg -> wire for various signals unneback 4447d 01h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v

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