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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_actel.v] - Rev 41

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Rev Log message Author Age Path
40 new build environment with custom.v added as a result file unneback 4998d 20h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
39 added simple port prio based wb arbiter unneback 4999d 17h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
38 updated andor mux unneback 4999d 17h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
37 corrected polynom with length 20 unneback 5005d 13h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
36 added generic andor_mux unneback 5006d 22h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
35 added vl_mux2_andor and vl_mux3_andor localparam unneback 5007d 09h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
34 added vl_mux2_andor and vl_mux3_andor unneback 5007d 09h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
33 updated wb3wb3_bridge unneback 5020d 11h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
32 added vl_pll for ALTERA (cycloneIII) unneback 5027d 21h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
31 sync FIFO updated unneback 5047d 16h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
30 updated counter for level1 and level2 function unneback 5047d 17h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
29 updated counter for level1 and level2 function unneback 5047d 17h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
28 added sync simplex FIFO unneback 5048d 18h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
27 added sync simplex FIFO unneback 5048d 18h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
25 added sync FIFO unneback 5049d 09h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
24 added vl_dff_ce_set unneback 5050d 17h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
23 fixed port map error in async fifo 1r1w unneback 5051d 07h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
22 added binary counters unneback 5051d 12h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
21 reg -> wire in and or mux in logic unneback 5052d 09h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
18 naming convention vl_ unneback 5053d 20h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v

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