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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_actel.v] - Rev 42

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42 updated mux_andor unneback 4802d 21h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
40 new build environment with custom.v added as a result file unneback 4802d 22h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
39 added simple port prio based wb arbiter unneback 4803d 19h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
38 updated andor mux unneback 4803d 20h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
37 corrected polynom with length 20 unneback 4809d 16h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
36 added generic andor_mux unneback 4811d 00h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
35 added vl_mux2_andor and vl_mux3_andor localparam unneback 4811d 12h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
34 added vl_mux2_andor and vl_mux3_andor unneback 4811d 12h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
33 updated wb3wb3_bridge unneback 4824d 14h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
32 added vl_pll for ALTERA (cycloneIII) unneback 4832d 00h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
31 sync FIFO updated unneback 4851d 19h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
30 updated counter for level1 and level2 function unneback 4851d 19h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
29 updated counter for level1 and level2 function unneback 4851d 19h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
28 added sync simplex FIFO unneback 4852d 21h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
27 added sync simplex FIFO unneback 4852d 21h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
25 added sync FIFO unneback 4853d 12h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
24 added vl_dff_ce_set unneback 4854d 19h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
23 fixed port map error in async fifo 1r1w unneback 4855d 10h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
22 added binary counters unneback 4855d 15h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
21 reg -> wire in and or mux in logic unneback 4856d 11h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
18 naming convention vl_ unneback 4857d 22h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
17 unneback 4921d 12h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
15 added delay line unneback 4927d 19h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
14 reg -> wire for various signals unneback 4928d 01h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
13 cosmetic update unneback 4928d 02h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
12 added wishbone comliant modules unneback 4928d 22h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
11 async fifo simplex unneback 4929d 13h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
10 added dff_ce_clear unneback 4931d 12h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
8 added dff_ce_clear unneback 4931d 12h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
7 mem update unneback 4931d 13h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v

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