URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_actel.v] - Rev 44

Rev	Log message	Author	Age	Path
22	added binary counters	unneback	4882d 12h	/versatile_library/trunk/rtl/verilog/versatile_library_actel.v
21	reg -> wire in and or mux in logic	unneback	4883d 08h	/versatile_library/trunk/rtl/verilog/versatile_library_actel.v
18	naming convention vl_	unneback	4884d 19h	/versatile_library/trunk/rtl/verilog/versatile_library_actel.v
17		unneback	4948d 08h	/versatile_library/trunk/rtl/verilog/versatile_library_actel.v
15	added delay line	unneback	4954d 16h	/versatile_library/trunk/rtl/verilog/versatile_library_actel.v
14	reg -> wire for various signals	unneback	4954d 21h	/versatile_library/trunk/rtl/verilog/versatile_library_actel.v
13	cosmetic update	unneback	4954d 23h	/versatile_library/trunk/rtl/verilog/versatile_library_actel.v
12	added wishbone comliant modules	unneback	4955d 19h	/versatile_library/trunk/rtl/verilog/versatile_library_actel.v
11	async fifo simplex	unneback	4956d 10h	/versatile_library/trunk/rtl/verilog/versatile_library_actel.v
10	added dff_ce_clear	unneback	4958d 08h	/versatile_library/trunk/rtl/verilog/versatile_library_actel.v