URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_actel.v] - Rev 45

Rev	Log message	Author	Age	Path
23	fixed port map error in async fifo 1r1w	unneback	4881d 20h	/versatile_library/trunk/rtl/verilog/versatile_library_actel.v
22	added binary counters	unneback	4882d 02h	/versatile_library/trunk/rtl/verilog/versatile_library_actel.v
21	reg -> wire in and or mux in logic	unneback	4882d 22h	/versatile_library/trunk/rtl/verilog/versatile_library_actel.v
18	naming convention vl_	unneback	4884d 09h	/versatile_library/trunk/rtl/verilog/versatile_library_actel.v
17		unneback	4947d 22h	/versatile_library/trunk/rtl/verilog/versatile_library_actel.v
15	added delay line	unneback	4954d 06h	/versatile_library/trunk/rtl/verilog/versatile_library_actel.v
14	reg -> wire for various signals	unneback	4954d 11h	/versatile_library/trunk/rtl/verilog/versatile_library_actel.v
13	cosmetic update	unneback	4954d 13h	/versatile_library/trunk/rtl/verilog/versatile_library_actel.v
12	added wishbone comliant modules	unneback	4955d 09h	/versatile_library/trunk/rtl/verilog/versatile_library_actel.v
11	async fifo simplex	unneback	4955d 23h	/versatile_library/trunk/rtl/verilog/versatile_library_actel.v